1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a fabricating method thereof that are capable of preventing a breakage of a pixel electrode.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) of active matrix driving system uses thin film transistors (TFT's) as switching devices to display a natural moving picture. Since such an LCD can be made into a smaller device in size than a CRT, it has been widely used as a monitor for a personal computer or a notebook computer, as well as in office automation equipment such as a copy machines, etc. and a portable equipment such as a cellular phone and a pager, etc.
Referring to FIG. 1 and FIG. 2, a lower substrate 1 of an LCD includes a thin film transistor (TFT) T arranged at crossing area of a data line 4 and a gate line 2, a pixel electrode 22 connected to a drain electrode 10 of the TFT, and a storage capacitor S positioned at an overlapping portion between the pixel electrode 22 and the previous gate line 2. FIG. 2 is a cross-sectional view taken along I-I′ of FIG. 1.
The TFT T includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected, via a first contact hole 20a, to the pixel electrode 22. Further, the TFT T includes semiconductor layers 14 and 16 for defining a channel between the source electrode 8 and the drain electrode 10 by a gate voltage applied to the gate electrode 6. Such a TFT T responds to a gate signal from the gate line 2 to selectively apply a data signal from the data line 4 to the pixel electrode 22.
The pixel electrode 22 is positioned at a cell area defined by the data line 4 and the gate line 2 and is made from a transparent conductive material having a high light transmissivity. The pixel electrode 22 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) from a data signal applied via the first contact hole 20a. By this potential difference, a liquid crystal positioned between the lower substrate 1 and the upper substrate (not shown) is rotated due to its dielectric anisotropy. Thus, the liquid crystal allows light applied from a light source to be transmitted into the upper substrate via the pixel electrode 22.
The storage capacitor S charges a voltage as a gate high voltage is applied to the previous gate line 2 and discharges the charged voltage as a data signal is applied to the pixel electrode to prevent a voltage variation in the pixel electrode 22. The storage capacitor S consists of a previous gate line 2 and a storage electrode 30 overlapping with the gate line 2 with a gate insulating film 12 therebetween. The storage capacitor S is electrically connected to the pixel electrode 22 via a second contact hole 20b defined at a protective film 18.
Such a lower substrate 1 of the LCD requires at least five masks for patterning each layer.
The gate electrode 6 is patterned with a first mask while the semiconductor layers 14 and 16 are patterned with a second mask. The storage electrode 30 and the source and drain electrodes 8 and 10 are patterned with a third mask while the first contact hole 20a, the second contact hole 20b and the protective layer 18 are patterned with a fourth mask. The pixel electrode 22 is patterned with a fifth mask.
FIG. 3A to FIG. 3E are sectional views for explaining a method of fabricating the LCD device shown in FIG. 2 step by step.
Referring first to FIG. 3A, the gate electrode 6 and the gate line 2 are provided on the substrate 1. The gate electrode 6 and the gate line 2 are formed by depositing aluminum (Al) or copper (Cu), etc. using a deposition technique such as a sputtering, etc. and then patterning it with the first mask.
Referring to FIG. 3B, an active layer 14 and an ohmic contact laser 16 are provided on a gate insulating film 12.
The active layer 14 and the ohmic contact layer 16 are formed by disposing the semiconductor layers 14 and 16 after forming the gate insulating film 12 on the substrate 1 in such a manner to cover the gate electrode 6 and then patterning them with the second mask.
The gate insulating film 12 is, formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) by the plasma enhanced chemical vapor deposition (PECVD) technique. The active layer 14 is formed from amorphous silicon that is not doped with an impurity. On the other hand the ohmic contact layer 16 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration.
Referring to FIG. 3C, the storage electrode 30 and the source and drain electrodes 8 and 10 are provided on the gate insulating film 12. The storage electrode 30 and the source and drain electrodes 8 and 10 are formed by entirely depositing a metal layer using the chemical vapor deposition (CVD) technique or the sputtering technique and then patterning it with the third mask. After the source and drain electrodes 8 and 10 are patterned, the ohmic contact layer 16 at an area corresponding to the gate electrode 6 also is patterned to expose the active layer 14. The area of the active layer 14 corresponding to the gate electrode 6 between the source and drain electrodes 8 and 10 makes a channel. The storage electrode 30 and the source and drain electrodes 8 and 10 are made from chrome (Cr) or molybdenum (Mo).
Referring to FIG. 3D, the protective layer 18 and the first and second contact holes 20a, 20b are provided on the gate insulating layer 12. The protective layer 18 and the first and second contact holes 20a, 20b are formed by depositing an insulating material on the gate insulating layer 12 in such a manner to cover the storage electrode 30 and the source and drain electrodes 8 and 10 and then patterning it with the fourth mask. The protective layer 18 is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), an acrylic organic compound, or an organic insulating material having a small dielectric constant such as Teflon, BCB (benzocyclobutene), Cytop or PFCB (perfluorocyclobutane).
Referring to FIG. 3E, the pixel electrode 22 is provided on the protective layer 18. The pixel electrode 22 is formed by depositing a transparent conductive material on the protective layer 18 and then patterning it with the fifth mask. The pixel electrode 22 is electrically connected to the drain electrode 10 via the first contact hole 20a and is electrically connected to the storage electrode 30 via the second contact hole 20b. The pixel electrode 22 is made from a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO).
Although such a lower substrate of the liquid crystal display device requires a five-step mask process, it additionally requires at least two masks for the purpose of preventing a hillock that may occur at an aluminum surface when the gate electrode is made from aluminum. Accordingly, a construction of the lower substrate of the liquid crystal displays device requires at least a five- to seven-step mask process.
As the number of masks increases, the number of processes and processing time not only increase when each layer is patterned, but also the productivity and the yield are reduced. For this reason, there has been actively conducted a study for reducing the number of masks.
FIG. 4 and FIG. 5 are a plan view and a sectional view, respectively, showing a lower substrate of the LCD employing a half-tone mask in a four-mask process.
Referring to FIG. 4 and FIG. 5 the lower substrate 1 of the LCD includes a thin film transistor (TFT) T arranged at a crossing area of a data line 4 and a gate line 2, a pixel electrode 22 connected to a drain electrode 10 of the TFT T, and a storage capacitor S positioned at an overlapping portion between the pixel electrode 22 and the previous gate line 2.
The TFT T includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22 via a contact hole 20. Further, the TFT T includes semiconductor layers 14 and 16 for defining a channel between the source electrode 8 and the drain electrode 10 by a gate voltage applied to the gate electrode 6. Such a TFT T responds to a gate signal from the gate line 2 to selectively apply a data signal from the data line 4 to the pixel electrode 22.
The pixel electrode 22 is positioned at a cell area defined by the data line 4 and the gate line 2 and is made from a transparent conductive material having a high light transmissivity. The pixel electrode 22 generates a potential difference from a common transparent electrode (not shown) provided at an upper substrate (not shown) from a data signal applied via the contact hole 20. By this potential difference, a liquid crystal positioned between the lower substrate 1 and the upper substrate (not shown) is rotated due to its dielectric anisotropy. Thus, the liquid crystal allows a light applied from a light source to be transmitted into the upper substrate via the pixel electrode 22.
The storage capacitor S charges a voltage as a gate high voltage is applied to the previous gate line 2, and discharges the charged voltage as a data signal is applied to the pixel electrode to prevent a voltage variation in the pixel electrode 22. The storage capacitor S consists of a previous gate line 2 and a storage electrode 30 overlapping with the gate line 2 with a gate insulating film 12 therebetween. The storage capacitor S is directly connected to the pixel electrode 22.
Such a lower substrate 1 of the LCD requires at least four masks for patterning each layer. The gate electrode 6 is patterned with a first mask, while an ohmic contact layer 16, the storage electrode 30 and the source and drain electrodes 8 and 10 are patterned with a second mask. The active layer 14, the contact hole 20 and the protective layer 18 are patterned with a third mask, while the pixel electrode 22 is patterned with a fourth mask.
Referring first to FIG. 6A, the gate line 2 and the gate electrode 6 are provided on the substrate 1. The gate line 2 and the gate electrode 6 are formed by depositing aluminum (Al) or copper (Cu) using a deposition technique such as a sputtering, etc. and then patterning it with the first mask.
Referring to FIG. 6B, the gate insulating film 12, the ohmic contact layer 16, the storage electrode 30 and the source and drain electrodes 8 and 10 are provided on the substrate 1. The gate insulating film 12 is formed by entirely depositing on the substrate 1 in such a manner to cover the gate electrode 6 and the gate line 2.
The ohmic contact layer 16, the storage electrode 30 and the source and drain electrodes 8 and 10 are formed by depositing a first semiconductor layer 14a, a second semiconductor layer and a metal layer on the gate insulating film 12 and then patterning the second semiconductor layer and the metal layer using the second mask. After the storage electrode 30 and the source and drain electrodes 8 and 10 are patterned, the ohmic contact layer 16 at an area corresponding to the gate electrode 6 also is patterned to expose the first semiconductor layer 14a. The area corresponding to the gate electrode 6 between the source and drain electrodes 8 and 10 at the first semiconductor layer 14a makes a channel.
The gate insulating film 12 is formed by depositing an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) by the plasma enhanced chemical vapor deposition (PECVD). The first semiconductor layer 14a, which is formed to be an active layer later, is formed from amorphous silicon that is not doped with on impurity. On the other hand, the ohmic contact layer 16 is formed from amorphous silicon doped with an n-type or p-type impurity at a high concentration. The storage electrode 30 and the source and drain electrodes 8 and 10 are formed from chrome (Cr) or molybdenum (Mo).
Referring to FIG. 6C, an insulating material 18a and a photoresist 24 are provided on the first semiconductor layer 14a. A half-tone mask 26 that is the third mask having a transmissive part 26a, a semi-transmissive part 26b and a shielding part 26c is positioned over the photoresist 24. The shielding part 26c is defined at an area later to be provided with the protective film 18 of the TFT; the transmissive part 26a is defined at an area later to be provided with the contact hole 20 of the TFT; and the semi-transmissive part 26b is defined at the remaining area.
The half-tone mask 26 selectively irradiates ultraviolet light to the photoresist 24 to expose it to the light.
The insulating material 18a is made from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), an acrylic organic compound, or an organic insulating material having a small dielectric constant such as Teflon, BCB (benzocyclobutene), Cytop or PFCB (perfluorocyclobutane).
Referring to FIG. 6D, a photoresist pattern 28 is formed on the insulating material 18a. The photoresist pattern 28 is formed by developing the photoresist 24 with a developer such as alkali aqueous solution. The photoresist pattern 28 having a thickness corresponding to approximately 10 to 50% of the initial coating thickness is formed at an area corresponding to the semi-transmissive part 26b of the half-tone mask 26. The photoresist pattern 28 having the initial coating thickness is formed at an area corresponding to the shielding part 26c. The photoresist pattern 28 is removed at an area corresponding to the transmissive part 26a to thereby expose the insulating material 18a. 
Referring to FIG. 6E, the active layer 14, the protective layer 18 and the contact hole 20 are provided on the gate insulating layer 12. The active layer 14, the protective layer 18 and the contact hole 20 are formed by exposing the lower substrate 1 provided with the photoresist pattern 28 to an etchant to simultaneously etch the insulating material 18a and the first semiconductor layer 14a. After the active layer 14, the protective layer 18 and the contact hole 20 are formed, the photoresist pattern 28 is removed.
Referring to FIG. 6F, the pixel electrode 22 is provided on the protective layer 18. The pixel electrode 22 is formed by depositing a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or indium-tin-zinc-oxide (ITZO) on the protective layer 18 and then patterning it using the fourth mask. The pixel electrode 22 is electrically connected to the drain electrode 10 via the contact hole 20, and is directly connected to the storage electrode 30 with no contact hole.
On the storage capacitor area S of the LCD, as shown in FIG. 6D, the photoresist pattern 28 is remained about 10 to 50 percents. After the contact hole 20 is formed, the area of the photoresist pattern 28 corresponding to the semi-transmissive part 26b of the half-tone mask 26 is removed by an ashing process. After all, the photoresist pattern 28 for forming the protective layer 18 and the active layer 14 are not provided on the storage capacitor area S. In other words, if the storage capacitor area S at the lower substrate 1 of the LCD is exposed to an etchant, then the protective layer 18 is entirely removed by the dry etching while the active layer 14 is left only at the lower portion of the storage electrode 30 formed by the wet etching. Since an eddy phenomenon is generated at the side surface of the active layer 14 when the active layer 14 is etched, the active layer 14 under the edge of the storage electrode 30 is more undercut than the storage electrode 30 to form a step coverage or an overhang, as shown in FIG. 7. If a transparent conductive material is deposited onto the gate insulating film 12 on which the active layer 14 is formed in the step coverage, the transparent conductive material is non-uniformly deposited at the step coverage area. For this reason, the conventional LCD has a problem in that, when the lower substrate 1 of the LCD is dipped into an etchant to etch the transparent conductive material, the pixel electrode 22 is susceptible to breakage at the step coverage area.